As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 22 nm or smaller dimensions, while the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. Recently, complementary metal oxide semiconductor (CMOS) FinFET devices have been introduced into many logic and other applications and are integrated into various different types of semiconductor devices.
FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed thereover. A gate electrode is then formed over and along side of a portion of the fin devices utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of FinFETs include reducing the short channel effect and providing higher current flow.
For epitaxial growth in narrow trenches, it is critical to trap the defects near the bottom of the trenches. The traditional flat bottom is (100) surface. The defect such as stacking faults and thread dislocations, especially for material such as GaAs or GaN, the antiphase boundary can propagate to the top portion of the semiconductor fins. The defects can cause device leakage and low performance.
Therefore, there is a need for an improved method to grow epitaxial materials in narrow trenches without having defects presented at the top portion of the semiconductor fins.